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1 of 14 112701 features real-time clock with fully compatible 1- wire ? microlan interface uses the same binary time/date representation as the ds2404 but with 1 second resolution clock accuracy 2 minutes per month at 25c communicates at 16.3kbits per second unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48- bit serial number + 8-bit crc tester) assures absolute traceability because no two parts are alike 8-bit family code specifies device communication requirements to bus master built-in multidrop controller ensures compatibility with other microlan products operates over a wide v dd voltage range of 2.5v to 5.5v from -40c to +85c low power, 200na typically with oscillator running compact, low cost 6-pin tsoc surface mount package pin assignment pin description pin 1 - gnd pin 2 - 1-wire pin 3 - v dd pin 4 - v bat pin 5 - x1 pin 6 - x2 ordering information ds2415p 6-pin tsoc package ds2415p/t&r tape & reel of ds2415p ds2415x chip scale pkg., tape & reel description the ds2415 1-wire time chip offers a simple solution for storing and retrieving vital time information with minimal hardware. the ds2415 contains a unique , lasered rom and a real-time clock/calendar implemented as a binary counter. only one pin is required for communication with the device. utilizing a backup energy source, the data is nonvolatile and a llows for stand-alone operation. the ds2415 features can be used to add functions such as calendar, time and date stamp, and logbook to any type of electronic device or embedded application that uses a microcontroller. overview the ds2415 has two main data com ponents: 1) 64-bit lasered rom, and 2) real-time clock counter (figure 1). the real-time clock utilizes an on-chip oscillator that is connected to an external 32.768khz crystal. all data is read and written least significant bit first. the real-time clock functions will not be ds2415 1-wire time chip www.maxim-ic.com 6-pin tsoc package top view downloaded from: http:///
ds2415 2 of 14 available until the rom function protocol has been established. this protocol is described in the rom functions flow chart (figure 7). the master must first provide one of four rom function commands: 1) read rom, 2) match rom, 3) search rom, 4) skip rom. after a rom function sequence has been successfully executed, the real-time clock functions are accessible and the master may then provide a real time clock function command (figure 5). detailed pin description pin symbol description 1 gnd ground pin. 21 - w i r e data input/output . open drain. 3v dd internal power line . connect a capacitor 4v bat power input pin . 2.5v to 5.5v. 5, 6 x1, x2 crystal pins. connections for a standard 32.768khz quartz crystal, epson part number c-002rx or c-004r (be sure to request 6pf load capacitance). note: x1 and x2 are very high-impedance nodes. it is recommended that they and the crystal be guard-ringed with ground and that high frequency signals be kept away from the crystal area. see figure 10 and application note 58 for details. block diagram figure 1 64-bit lasered rom each ds2415 contains a unique rom code that is 64 bits long. the first 8 bits are a 1-wire family code. the next 48 bits are a unique serial number. the last 8 bits are a crc of the first 56 bits. (see figure 3.) the 1-wire crc of the lasered rom is generated using the polynomial x 8 + x 5 + x 4 + 1. additional information about the dallas semic onductor 1-wire cyclic redundancy ch eck is available in the book of ds19xx ibutton standards ? . the 64-bit rom and rom function control section allow the ds2415 to operate as a 1-wire device and follow the 1-wire pr otocol detailed in the section 1-wire bus system. downloaded from: http:///
ds2415 3 of 14 the functions required to exercise the control f unctions of the ds2415 are not accessible until the rom function protocol has been satisfi ed. this protocol is described in the rom functions flow chart (figure 7). the 1-wire bus master must first provi de one of the four rom function commands. after a rom function sequence has been successfully execute d, the bus master may then provide one of the function commands specific to the ds2415 (figure 5). hierarchical structure for 1-wire protocol figure 2 64-bit lasered rom figure 3 msb lsb 8-bit crc code 48-bit serial number 8-bit family code (24h) msb lsb msb lsb msb lsb 1-wire crc generator figure 4 polynomial = x 8 + x 5 + x 4 + 1 downloaded from: http:///
ds2415 4 of 14 timekeeping a 32.768khz crystal oscillator is used as the time base for the real-time clock counter. the oscillator can be turned on or off under software control. the osc illator must be on for the re al-time clock to function. the real-time clock counter is double-buffered. this allows the master to r ead time without the data changing while it is being read. to accomplish this, a snapshot of the counter data is transferred to a read/write buffer, which the user accesses. device control byte the on/off control of the 32.768khz crystal oscillator is done through the device control byte. this byte can be read and written through the clock function commands. device control byte 76543210 u4 u3 u2 u1 osc osc 0 0 bit 0 - 1 0 no function bits 0 and 1 are hard-wired to read all 0s. bit 2 - 3 osc oscillator enable/disable these bits control/report whether the 32.768khz crystal oscillator is running. if the oscillator is running, both osc bits will read 1. if the oscillator is turned off these bits will read 0. when writing the device control byte both occurrences of the osc bit should have identical data. otherwise, the value in bit address 3 (bold) takes precedence. bit 4 - 7 un general-purpose user flags these bits have no particular func tion within the chip. they can be read and written under the control of the application software and rema in non-volatile as long as there is sufficient voltage at the v dd pin. if the ds2415 is located inside a battery pack, for exam ple, these bits could convey data on the charging status from the charging station to the equipment that uses the battery. real-time clock the real-time clock is a 32-bit binary counter. it is incremented once per second. the real-time clock can accumulate 136 years of seconds before rolling over. time/date is represented by the number of seconds since a reference point, which is determined by th e user. for example, 12:00 a.m., january 1, 1970 could be a reference point. clock function commands the clock function flow chart (figure 5) describes the protocols necessary for accessing the real -time clock. with only four bytes of r eal-time clock and one control by te the ds2415 does not provide random access. reading and writing always starts with the device control byte followed by the least significa nt byte (lsb) of the time data. downloaded from: http:///
ds2415 5 of 14 read clock [66h] the read clock command is used to read the device c ontrol byte and the contents of the real-time clock counter. after having received the most significant b it of the command code the device copies the actual contents of the real-time clock counter to the read/w rite buffer. now the bus master reads data beginning with the device control byte followed by the least significant byte through the most significant byte of the real-time clock. after this the bus master may continue reading from the ds2415. the data received will be the same as in the first pass through the co mmand flow. the read clock command can be ended at any point by issuing a reset pulse. write clock [99h] the write clock command is used to set the real-time clock counter and to write the device control byte. after issuing the command, the bus master writes first the device control byte, which becomes immediately effective. after this the bus master sends the least significant byte through the most significant byte to be written to the real time cl ock counter. the new time da ta is copied from the read/write buffer to the real time clock counter and becomes effective as the bus master generates a reset pulse. if the oscillator is intentionally stopped the real time clock counter behaves as a 4-byte nonvolatile memory. downloaded from: http:///
ds2415 6 of 14 clock function command flow chart figure 5 downloaded from: http:///
ds2415 7 of 14 hardware configuration figure 6 1-wire bus system the 1-wire bus is a system that has a single bus master and one or more slaves. in all instances the ds2415 behaves as a slave. the discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-wire signaling (signal ty pes and timing). a 1-wire protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falling edge of sync pulses from the bus master. for a more detailed protocol description, refer to chapter 4 of the book of ds19xx ibutton standards. hardware configuration the 1-wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have open drain or 3-state outputs. the 1-wire input of the ds2415 is open drain w ith an internal circuit equivalent to that shown in figure 6. a multidrop bus consists of a 1-wire bus with multiple slaves attached. the 1- wire bus has a maximum data rate of 16.3kbits per second and requires a pullup resistor of approximately 5k . the idle state for the 1-wire bus is high. if for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 120 s, one or more of the devices on the bus may be reset. since the ds2415 gets all its energy for operation through its v bat pin it will not perform a power-on reset if the 1-wire bus is low for an extended time period. transaction sequence the protocol for accessing the ds2415 vi a the 1-wire port is as follows: initialization rom function command clock function command downloaded from: http:///
ds2415 8 of 14 initialization all transactions on the 1-ire bus begin with an initialization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that th e ds2415 is on the bus and is ready to operate. for more details, see the 1-wire signaling section. rom function commands once the bus master has detected a presence, it ca n issue one of the four rom function commands. all rom function commands are 8 bits long. a list of these commands follows (refer to flowchart in figure 7): read rom [33h] this command allows the bus master to read the ds2415s 8-bit family code, unique 48-bit serial number, and 8-bit crc. this command can only be used if there is a single ds2415 on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wire d-and result). the resultant family code and 48-bit serial number will usually result in a mismatch of the crc. match rom [55h] the match rom command, followed by a 64-bit rom sequence, allows the bus master to address a specific ds2415 on a multidrop bus. only the ds2415 th at exactly matches the 64-bit rom sequence will respond to the following clock function comma nd. all slaves that do not match the 64-bit rom sequence will wait for a reset pulse. this command can be used with a single or multiple devices on the bus. skip rom [cch] this command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit rom code. if more than one slave is present on the bus and a read command is issued following the skip rom command, data collision will occur on the bus as multiple slaves transmit simultaneously (open dr ain pulldowns will produce a wired-and result). search rom [f0h] when a system is initially brought up, the bus master might not know the number of devices on the 1- wire bus or their 64-bit rom codes. the search rom command allows the bus master to use a process of elimination to identify the 64-bit rom codes of all slave devices on the bus. the search rom process is the repetition of a simple, three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this simple, three-step routine on each bit of the rom. after one complete pass, the bus master knows the contents of the rom in one device. the remaining number of devices and their rom c odes may be identified by additiona l passes. see chapter 5 of the book of ds19xx ibutton standards for a comprehensive discussion of a search rom, including an actual example. downloaded from: http:///
ds2415 9 of 14 rom functions flow chart figure 7 downloaded from: http:///
ds2415 10 of 14 1-wire signaling the ds2415 requires strict protocols to insure data integrity. the prot ocol consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1, and read data. the bus master initiates all these signals, except presence pulse. the initialization sequence required to begin any communication with the ds2415 is shown in figure 8. a reset pulse followed by a presence pulse indicates the ds2415 is ready to se nd or receive data given the correct rom command and control function command. the bus mast er transmits (tx) a reset pulse (t rstl , minimum 480 s). the bus master then releases the line and goes into receive mode (rx). the 1-wire bus is pulled to a high state via the pullup resistor. after detecting the rising edge on the data line, the ds2415 waits (t pdh , 15 s to 60 s) and then transmits the presence pulse (t pdl , 60 s to 240 s). initialization procedure reset and presence pluses figure 8 480 s t rstl < * 480 s t rsth < ( includes recovery time) 15 s t pdh < 60 s 60 s t pdl < 240 s in order not to mask interrupt signalin g by other devices on the 1-wire bus, t rstl + t r should always be less than 960 s. read/write time slots the definitions of write and read time slots are illustrated in figure 9. all time slots are initiated by the master driving the data line low. the falling edge of the data line synchronizes the ds2415 to the master by triggering a delay circuit in the ds2415. during write time slots, the delay circ uit determines when the ds2415 will sample the data line. for a read data time slot, if a 0 is to be transmitted, the delay circuit determines how long the ds2415 will hold the data line low overriding th e 1 generated by the master. if the data bit is a 1, the device will leave the read data time slot unchanged. resistor master ds2415 downloaded from: http:///
ds2415 11 of 14 read/write timing diagram figure 9 write-1 time slot 60 s t slot < 120 s 1 s t low1 < 15 s 1 s t rec < write-0 time slot 60 s t low0 < t slot < 120 s 1 s t rec < downloaded from: http:///
ds2415 12 of 14 read-data time slot 60 s t slot < 120 s 1 s t lowr < 15 s 0 t release < 45 s s t rec < t rdv = 15 s t su < 1 s crystal placement on pcb figure 10 local ground plane beneath signal plane or on other side of pcb resistor master ds2415 downloaded from: http:///
ds2415 13 of 14 absolute maximum ratings* voltage on 1-wire to ground -0.5v to +7.0v operating temperature range -40 c to +85 c storage temperature range -55 c to +125 c soldering temperature see j-std-020a specification this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. the dallas semiconductor ds2415 is built to the highes t quality standards and manufactured for long term reliability. all da llas semiconductor devices are made using the same quality materials and manufacturing methods. however, the ds2415 is not exposed to environmental stresses, such as burn-in, that some industrial app lications require. for specific relia bility information on this product, please contact the factory in dallas at (972) 371-4448. dc electrical characteristics (-40c to +85c, v pup = 2.5v to 6.0v, v bat = 2.5v to 5.5v) parameter symbol min typ max units notes logic 1 v ih1 2.2 6.0 v 1,12 logic 0 v il1 -0.3 +0.8 v 1,7 output logic low @ 4ma v ol1 0.4 v 1 output logic high v oh1 v pup v 1,3 input load current i l1 5 a 4 operating current (osc. on) i bat3 250 na 2,10 quiescent current (osc. off) i batq3 50 na 2,9,10 operating current (osc. on) i bat5 450 na 2,11 quiescent current (osc. off) i batq5 100 na 2,9,11 capacitance (t a = 25c) parameter symbol min typ max units notes capacitance 1-wire c in 50 pf downloaded from: http:///
ds2415 14 of 14 ac electrical characteristics (-40c to +85c, v pup = 2.5v to 6.0v, v bat = 2.5v to 5.5v) parameter symbol min typ max units notes time slot t slot 60 120 s write 1 low time t low1 11 5 s 14 write 0 low time t low0 60 120 s read low time t lowr 11 5 s 14 read data valid t rdv 15 s 13 release time t release 01 54 5 s read data setup t su 1 s 6 recovery time t rec 1 s reset time high t rsth 480 s 5 reset time low t rstl 480 960 s 8 presence detect high t pdh 15 60 s presence detect low t pdl 60 240 s notes:1. all voltages are referenced to ground. 2. measured with outputs open. 3. v pup = external pullup voltage. 4. input load is to ground. 5. an additional reset or communica tion sequence cannot begin until th e reset high time has expired. 6. read data setup time refers to the time the bus master must pull the i/o line low to read a bit. data is guaranteed to be valid within 1 s of this falling edge. 7. under certain low voltage conditions v il1max may have to be reduced to as much as 0.5v to always guarantee a presence pulse. 8. the reset low time (t rstl ) should be restricted to a maximum of 960 s, to allow interrupt signaling, otherwise, it could mask or conceal interrupt pulses. 9. when v bat ramps up, the oscillator is always off. 10. at v bat = 3v 10% 11. at v bat = 5v 10% 12. v ih1 has to be v bat -0.3v or higher. 13. the optimal sampling point for the master is as close as possible to the end time of the 15s t rdv period without exceeding t rdv . for the case of a read-one time slot, this maximizes the amount of time for the pull-up resistor to recover to a high level. for a read-zero time slot, it ensures that a read will occur before the fastest 1-wire device(s) release the line. 14. the duration of the low pulse sent by the master should be a minimum of 1s with a maximum value as short as possible to allow time for the pull-up resistor to recover the line to a high level before the 1-wire device samples in the case of a write-one time or before the master samples in the case of a read-one time. downloaded from: http:///

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